Automated Design of Wave Pipelined Multiport Register Files
نویسندگان
چکیده
| Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register les are generally used. However, conventional multiport register les need a considerable amount of hardware. This paper proposes a multiport register le scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy bu ers into combinatorial logic.
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